New PDF release: Advanced Memory Optimization Techniques for Low Power

By Manish Verma, Peter Marwedel

ISBN-10: 1402058969

ISBN-13: 9781402058967

This booklet proposes novel reminiscence hierarchies and software program optimization thoughts for the optimum usage of reminiscence hierarchies. It offers quite a lot of optimizations, steadily expanding within the complexity of research and of reminiscence hierarchies. the ultimate bankruptcy covers optimization thoughts for purposes such as a number of techniques present in newest embedded devices.

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Extra resources for Advanced Memory Optimization Techniques for Low Power Embedded Processors

Sample text

After having decided that both code segments and global variables should be considered as memory objects, we would like quantify the energy reduction that could be achieved by allocating the memory objects onto the scratchpad memory. Let us assume that we have a memory hierarchy consisting of a 512 bytes onchip scratchpad and a 64k bytes main memory. Additionally, assume that we have a simple per access energy model (cf. 2) for the memories. e. each instruction is 2 bytes or 16 bits wide. Therefore, the energy consumed by the memory hierarchy when the scratchpad memory is not utilized is 2, 939, 787∗10+203, 694∗20 = 33, 471, 750 units.

Processor Address Space Containing a Scratchpad Memory energy consumption of the system executing the application is minimized. The mapping should be done under the constraint that the aggregate size of memory objects mapped to the scratchpad memory should be less than the size of the memory. The proposed approaches use an accurate energy model which, based on the number and the type of accesses originating from a memory object and the target memory, compute the energy consumed by the memory object.

9. Normalized Energy Comparison of Scratchpad Allocation Approaches and therefore, the larger is the reduction in the total energy consumption of the system. The SA approach achieves a maximum total energy reduction of 71%, 84%, 87% and 88% for main memories with 1, 5, 10 and 20 master clock latencies, respectively. 3 M5 DSP The M5 DSP in its default configuration contains a large onchip group memory to hold the data variables. The energy dissipation of the data memory hierarchy is improved by inserting a small and energy efficient L1 scratchpad or group memory.

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Advanced Memory Optimization Techniques for Low Power Embedded Processors by Manish Verma, Peter Marwedel


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